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Honored Contributor
Honored ContributorStratix IV and DDR3
Has anyone done a Stratix IV design with DDR3? I've got a little test project set up. The DDR3 controller is instantiated inside SoPC builder. During synthesis the following error is given: E...
Altera_ForumHonored Contributor
Honored ContributorHi,
i have the same problem with my DDR3 HPFII controller. But your solution doesn't help me. The clock pins from the controller are bidirectional on the toplevel. I check with Quartus II RTL viewer and the pins are bidirectional too. I had an old compalation with these HPF Controller an singla rank sodimm, there was no error. Now an sodimm with dual rank this error is shown. Maybe the memory preset is wrong. The sodimm has 2 chip selects. Each for 1 rank. I try this: Total Memory chip selects : 2 Chip selects per DIMM : 2 Chip selects per rank : 2 Is this right? Regards Josef
