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Altera_Forum's avatar
Altera_Forum
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16 years ago

Stratix IV and DDR3

Has anyone done a Stratix IV design with DDR3? I've got a little test project set up. The DDR3 controller is instantiated inside SoPC builder. During synthesis the following error is given: E...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

I'm also doing the same thing as you did (my mem_bot_clk and mem_bot_clk_n are already in inout mode) in my top level entity but I still have the

"...also drives out to other destination than the buffer" message.

I also checked out the altera solution which is to convert each std_logic_vector(0 downto 0) into std_logic but it seems useless.

I'm actually using Quartus II 11.0 Full Version with a Stratix IV GX 230 and I'm trying to use the Triple Speed Ethernet.

My design worked fine with a Nios II until I decided to add two SGDMA (RX and TX) and the TSE core. (after that my Nios II seems to be turned off but the design still work with signaltap, I use the Nios II only for the printf() )

And my question is, does anyone know how to solve the DDR3 problem with Quartus II 11.0 ?

Best regards,

Michel