New ContributorHi all,
I've just migrated my Quartus Prime Pro project from 19.1 to 19.4 and noticed that in the newer version, the Stratix 10 PCIe HIP wants me to connect something to the "ninit_done" input signal. It looks like this signal is related to the Native PHY Debug Master Endpoint (NPDME). If I don't use NPDME in my design, can I just tie the ninit_done signal to 0?
Frequent ContributorHi Sir,
The ninit_done is introduced due new configuration scheme is needed in Stratix 10 device.
See the configuration handbook and diagram as below. It is better if you can include the reset IP in your design and connect the ninit_done from the reset IP to the input of the PCIe Ip.
Hope this helps.
Frequent ContributorThe description of this signals also included in the PCIe UG.
https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf#page158
Active-low output signal from the Reset Release Intel FPGA IP. High indicates that the FPGA device is not yet fully configured, and low indicates the device has been configured and is in normal operating mode. For more details on the Reset Release Intel FPGA IP, refer to https:// www.intel.com/content/www/us/en/ programmable/documentation/ prh1555609801770.html
New ContributorI see. That's useful information. So this new reset-release IP has no input signals, and only exports the ninit_done signal, correct?
Frequent ContributorHi Sir,
Yes, it only have one output. Basically this IP will monitor the configuration status of the FPGA and only release the reset to user after everything is ready.
