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User1573261788318367's avatar
User1573261788318367
Icon for New Contributor rankNew Contributor
6 years ago

Stratix 10 PCIe HIP ninit_done

Hi all, I've just migrated my Quartus Prime Pro project from 19.1 to 19.4 and noticed that in the newer version, the Stratix 10 PCIe HIP wants me to connect something to the "ninit_done" input signa...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Sir,

Yes, it only have one output. Basically this IP will monitor the configuration status of the FPGA and only release the reset to user after everything is ready.