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User1573261788318367's avatar
User1573261788318367
Icon for New Contributor rankNew Contributor
6 years ago

Stratix 10 PCIe HIP ninit_done

Hi all, I've just migrated my Quartus Prime Pro project from 19.1 to 19.4 and noticed that in the newer version, the Stratix 10 PCIe HIP wants me to connect something to the "ninit_done" input signa...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

The description of this signals also included in the PCIe UG.

https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf#page158

Active-low output signal from the Reset Release Intel FPGA IP. High indicates that the FPGA device is not yet fully configured, and low indicates the device has been configured and is in normal operating mode. For more details on the Reset Release Intel FPGA IP, refer to https:// www.intel.com/content/www/us/en/ programmable/documentation/ prh1555609801770.html