Strange and random (!?) error of the Control block

This is a bug. Are you absolutely sure that this only occurred after changing the Control block path? I would be surprised if that caused it.

It's most likely occurring where an Adder feeds a Mux. Look at the blocks around Subsystem1/Subsystem/Mux in your design. Have you hard-coded the types on any blocks in this area? Perhaps you can pare down the design so that it only contains a few blocks and yet has this problem. If you can, please post it here.

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This is a bug. Are you absolutely sure that this only occurred after changing the Control block path? I would be surprised if that caused it.

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99% sure.

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It's most likely occurring where an Adder feeds a Mux. Look at the blocks around Subsystem1/Subsystem/Mux in your design. Have you hard-coded the types on any blocks in this area? Perhaps you can pare down the design so that it only contains a few blocks and yet has this problem. If you can, please post it here.

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I cant post the whole design but I posted where the error occurs, for 'hard-coded' do you mean if I defined the output type mode for each block without using the "Inherit via internal rule"?

If you do, yes, I did hard-code them.

ps: the multiplier is treating complex data

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I cant post the whole design but I posted where the error occurs, for 'hard-coded' do you mean if I defined the output type mode for each block without using the "Inherit via internal rule"?

If you do, yes, I did hard-code them.

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Could you post that picture again, but with types shown and ideally the other block that feeds the mux. You can show the types using the Format Menu. Select "Port/Signal Displays" -> "Port Data Types". If the types don't show up then, you need to refresh your model. Press Ctrl + D to do that.

(and yes that's what I meant by hard-code them)

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Could you post that picture again, but with types shown and ideally the other block that feeds the mux. You can show the types using the Format Menu. Select "Port/Signal Displays" -> "Port Data Types". If the types don't show up then, you need to refresh your model. Press Ctrl + D to do that.

(and yes that's what I meant by hard-code them)

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Problem solved, I realized that the file of the Edit Param block was not in the right directory, after having fixed this the problem disappeared.

Ok it was my fault that I didnt move the file .m , but to understand this reading that error it was not so straightforward :D

Mmm, the problem appeared again, I was hard-coding the types then I tried to simulate the design and the error reappeared

I have attached the design with the data type, in this case only the output of the Mux is fixed, the rests are 'inhrited'

Quick update: I have found that if the output of that Mux is bigger than 36bits the design does not work, is there any way to overcome this problem ? (the full design is quite small so I would prefer to not break down it)

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Try using a Convert block with rounding and saturation disabled to reduce the bitwidth before the mux. I would also put a convert block after the multiplier before the delay to do the same thing.

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cool, thanks!

Im facing a similar error in another design:

Altera DSP Builder Advanced Internal Restriction: 'inPort.m_inWidth <=WIDE_MAX_DATAWIDTH'. Error in block '...Subsystem/tdm_Mux_coef_2_re_c' in mip_common/hw_fu.cpp:1299.

Error in '.../Control' while executing C MEX S-function 'mip_control', (mdlStart), at time 0. MATLAB error message:

Altera DSP Builder Advanced Internal Restriction: 'inPort.m_inWidth <= WIDE_MAX_DATAWIDTH'. Error in block '.../Subsystem/tdm_Mux_coef_2_re_c' in mip_common/hw_fu.cpp:1299.

I get the same error for 3 mux, 2 of them feeding the same multiplier and another one feeding another mux.

I have tried the solution of the Convert block to descrease the datawidth, even if i could not but i wanted just to check if it would work or not, but at the end i get the same error.

I get also a funny thing, let's say i have Mux1, Mux2, Mux3, if I add the convert blocks to Mux1 then I get error on the Mux2, if I add them also to Mux2 I get the error on the Mux3, if every Mux has the convert blocks I get the error again on the Mux1 !

Any of them has loops.

Thanks!

WIDE_MAX_DATAWIDTH is 512 so something is trying to generate a signal that's more 512 bits wide. If you're doing that then that's your problem.

If you don't have any signals that wide, then you're going to have to post a cut down version of your design so I can see what's going on. Ideally please post an MDL file.

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WIDE_MAX_DATAWIDTH is 512 so something is trying to generate a signal that's more 512 bits wide. If you're doing that then that's your problem.

If you don't have any signals that wide, then you're going to have to post a cut down version of your design so I can see what's going on. Ideally please post an MDL file.

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I dont have signals wider then 512 bits.

I have posted what I can, that Mult is feeding an adder, I have hard-coded almost all the data type, so I really dont know why it's happening.

Is there any check that I could do?

Thanks a lot!