Significance of the Descriptor_ID field used by the the PCIe-Avalon-MM-DMA IP core?

Hi ,

Can you please find the description of descriptor ID from the below document and , user have the access to write the decriptor ID from 0 to 127.

Page no: 9

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an708.pdf

Hello RahulS_Intel,

Thanks for your reply.

I read page 9 in the doc as you instructed. Unfortunately, it didn't answer my question. My question was about the rationale of the design decision for having a Descriptor_ID field in the descriptor table. I think the field is unnecessary. This is because the offset of a descriptor from the Descriptor Base Address already gives its ID. For example, the Status portion (with "Done" bits) of the Descriptor Table does not need a Descriptor_ID field. Please see the excerpt below.

What happens if the application logic writes a "1" to the Descriptor_ID field of Descriptor 0? To start the Read DMA process for this descriptor, should the application logic writes "1" or "0" to RD_DMA_LAST_PTR ?

Thanks,

Ari

Hi ,

Let me know , you need further assistance

Hi RahulS,

I don't have any more questions, for now. Thank you very much for your help.

Ari

Hi ,

Really glad to know .

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