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Arintel's avatar
Arintel
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5 years ago
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Significance of the Descriptor_ID field used by the the PCIe-Avalon-MM-DMA IP core?

Hi Everyone, Please see the 0x10 - Control register in Table 69 at this link, https://www.intel.com/content/www/us/en/programmable/documentation/lbl1415138844137.html#nik1410905615225 What is the p...
  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    5 years ago

    Hi ,

    In a way your pointer is correct and the descriptor id is written by software,

    should the application logic writes "1" or "0" to RD_DMA_LAST_PTR ?

    >>1

Arintel's avatar
Arintel
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5 years ago

Hello RahulS_Intel,

Thanks for your reply.

I read page 9 in the doc as you instructed. Unfortunately, it didn't answer my question. My question was about the rationale of the design decision for having a Descriptor_ID field in the descriptor table. I think the field is unnecessary. This is because the offset of a descriptor from the Descriptor Base Address already gives its ID. For example, the Status portion (with "Done" bits) of the Descriptor Table does not need a Descriptor_ID field. Please see the excerpt below.

What happens if the application logic writes a "1" to the Descriptor_ID field of Descriptor 0? To start the Read DMA process for this descriptor, should the application logic writes "1" or "0" to RD_DMA_LAST_PTR ?

Thanks,

Ari