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Arintel
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5 years ago
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Significance of the Descriptor_ID field used by the the PCIe-Avalon-MM-DMA IP core?

Hi Everyone, Please see the 0x10 - Control register in Table 69 at this link, https://www.intel.com/content/www/us/en/programmable/documentation/lbl1415138844137.html#nik1410905615225 What is the p...
  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    5 years ago

    Hi ,

    In a way your pointer is correct and the descriptor id is written by software,

    should the application logic writes "1" or "0" to RD_DMA_LAST_PTR ?

    >>1

Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi ,

In a way your pointer is correct and the descriptor id is written by software,

should the application logic writes "1" or "0" to RD_DMA_LAST_PTR ?

>>1