set_multicycle_path -setup & -hold for the flash_data[*] or set_max_delay or set_input_delay ?

I have a PFL (within CPLD MAX V) interfacing with the flash device and FPGA (Cyclone V)

Do we need to set_multicycle_path -setup & -hold for the flash_data[*] ?

Does it take multiple clock cycles to perform each operation ?

eg

set_multicycle_path -setup -to [get_ports {flash_data[*]}] 4
set_multicycle_path -hold -to [get_ports {flash_data[*]}] 3

Note: Numbers used above are arbitrary.

If yes, How do I determine how many cycles it takes for each operation?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

1.4.2.4. Summary of PFL Timing Constraints Table 7. PFL Timing Constraints

flash_data

Normal read mode: set_false_path • Burst read mode: set_input_delay

https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html

1.4.2.4. Summary of PFL Timing constraints

flash_data

Read mode (PFL to Flash ROM) set_max_delay -from <port> to pfl_clk Write mode (Flash ROM to PFL) set_false_path

2 docs above (as raised in another private message wrt other PFL signals too) show differences in constraints suggestions.

So far chosen the 2nd document (sss1411439280066.html) suggestion.

But maybe Multicycle paths should be used instead. Please comment here for both write mode and read mode cases.