Forum Discussion
Knug
Contributor
5 years agoset_multicycle_path -setup & -hold for the flash_data[*] or set_max_delay or set_input_delay ?
I have a PFL (within CPLD MAX V) interfacing with the flash device and FPGA (Cyclone V)
Do we need to set_multicycle_path -setup & -hold for the flash_data[*] ?
Does it take multiple clock cycles...
KennyT_altera
Super Contributor
5 years agoAny reason that you want to set Multi cycle? Usually, we do that because we have hard time closing timing.
You can check the waveforms behavior in your timing analyzer after setting it, It would be same as gate level simulation.