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Knug's avatar
Knug
Icon for Contributor rankContributor
5 years ago

set_multicycle_path -setup & -hold for the flash_data[*] or set_max_delay or set_input_delay ?

I have a PFL (within CPLD MAX V) interfacing with the flash device and FPGA (Cyclone V) Do we need to set_multicycle_path -setup & -hold for the flash_data[*] ? Does it take multiple clock cycles...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

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