Honored ContributorI'm using the Stratix II GX Serdes in Basic mode with 1600Mbps data rate and input clock equal to 80MHz for 16 bit data packet. In the receiving interface, duiring the operative condition, sometimes the received data seems to be swapped (eg. CDAB instead of ABCD). Can someone help me ? Thank you, Max.
Honored ContributorHi,
Since the receiver has no info about which two bytes come together, the byte swap may or may not happen. If there is a specific pattern to tell which the MSB or the LSB are, the receiver with byte-ordering can reorder them. Please look at s2gx handbook volume 2 page 2-113.Honored ContributorHi gee,
Thank you for your answer. I trry to explain better my issue. I send a 16-bit pattern but every 8-bit represent for me a channel (LS & HS from the antennas). So, I cannot send a known pattern to the Rx during the operative condition of the system cause I don't know if I'm receiving the correct pattern or not. have you any suggestion ?Honored ContributorHello,
I'm sorry. I misunderstood your problem. In such a case I have no idea to recover the original order. Is it impossible for you to make the internal bus 8bits instead of 16bits?Honored ContributorHi gee,
Tahnk you again for your support. So, talking with my colleagues, it seems that the problem could be the different clock jitter between the Rx and the Tx sections. Actually I'm trying to put into the Rx section the Rate Match FIFO but I've seen that I can use this feature only if I use the SerDes block with Tx&Rx interface; but I need only the Rx interface. Do you think the Rate Match FIFO could be a possible solution ? Have you used the Rate Match FIFO in the Rx SerDes ? Bye, Max.Honored ContributorHi,
I think that whether byte swap occurs or not only depends on undeterministic timing, such as reset deassertion or pll lock, so the rate match fifo would not work. Isn't there any way that you can figure out which byte should be placed lower? If no, the transceiver block can't tell it either.
