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Altera_Forum
Honored Contributor
Honored ContributorSerDes 8-bit Swap
I'm using the Stratix II GX Serdes in Basic mode with 1600Mbps data rate and input clock equal to 80MHz for 16 bit data packet. In the receiving interface, duiring the operative condition, sometimes ...
Altera_ForumHonored Contributor
Honored ContributorHi gee,
Tahnk you again for your support. So, talking with my colleagues, it seems that the problem could be the different clock jitter between the Rx and the Tx sections. Actually I'm trying to put into the Rx section the Rate Match FIFO but I've seen that I can use this feature only if I use the SerDes block with Tx&Rx interface; but I need only the Rx interface. Do you think the Rate Match FIFO could be a possible solution ? Have you used the Rate Match FIFO in the Rx SerDes ? Bye, Max.
