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Altera_Forum
Honored Contributor
Honored ContributorSerDes 8-bit Swap
I'm using the Stratix II GX Serdes in Basic mode with 1600Mbps data rate and input clock equal to 80MHz for 16 bit data packet. In the receiving interface, duiring the operative condition, sometimes ...
Altera_ForumHonored Contributor
Honored ContributorHi,
I think that whether byte swap occurs or not only depends on undeterministic timing, such as reset deassertion or pll lock, so the rate match fifo would not work. Isn't there any way that you can figure out which byte should be placed lower? If no, the transceiver block can't tell it either.
