RGMII with the triple speed ethernet MAC core

Hello liangbowen, as i see, i also work with TSE and marvell PHY.

Now i have workable transmit part from nios to PC, but i have some problems with receiving of packet.

So i can help you with transmit and you can help me with receive.

My configuration is:

Q 8.1 SP1 nios II 8.1

TSE

Marvell 88e1111

I send packets from nios through the MAC level and i want to receive it the same way from the PC.

At first it would be great to now how you made the receive of packet?

i try to make it by alt_avalon_sgdma_register_callback which will be launched after the packet came to PHY->MAC.

But i can't make it to step into the isr function in debug mode, i don't know what is the problem...

So i'll answer all your questions.

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Yes, but remember the TSE MAC only works for RGMII Gigabit mode but not RGMII 10/100 mode for now.

Information on setting the timing of RGMII interface

6.2.1 Receive Direction

The FPGA can accept clock edge aligned input data by adding pin-delay to the data inputs

ensuring proper DDR sampling. This can be achieved by applying negative hold-time

constraints (e.g. -1.5ns) to the data input pins of the FPGA.

If the pin-delay should not be used, alternatively the PHY can be instructed to add delay to its clock output pin by setting bit 7 of the MDIO register 20. To do so, the following procedure should be followed:

• read register 20

• set bit 7 to enable rx clock pin output delay preserving all other bits

• write register 20

• Issue a software reset to the phy to apply the change, by reading register 0

(CONTROL) and writing it back with bit 15 (reset) set to 1.

6.2.2 Transmit Direction

A typical DDR output implementation supporting multiple speeds in RGMII will provide the

clock edge aligned with the data edge. However, as the board does not implement a board

trace delay, the clock needs to be shifted by 2ns to ensure proper timing at the PHY device

inputs.

This can be done by either implementing a corresponding shift in the FPGA, or by setting the integrated delay transmit option (bit 1) within the MDIO register 20 of the PHY. To set the transmit delay option, the following procedure should be followed.

• read register 20

• set bit 1 to enable tx clock pin input delay preserving all other bits

• write register 20

• Issue a software reset to the phy to apply the change, by reading register 0 (CONTROL) and writing it back with bit 15 (reset) set to 1.

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Hello,

Can we apply these suggested steps on Cyclone III (C120)?

Thanks

I'm using the Altera Triple Speed Ethernet IP with cyclone iii, and trying to test the Rx and Tx of 10/100/1000 Ethernet MAC(RGMII). The test is done as following:

1- setting the loop_ENA bit in command_config register to 1 and

2-comparing the statistics counters aFramesTransmittedOK and

aFramesReceivedOK to verify that the transmit and receive frame counts are equal.

3-checking the statistics counters ifInErrors and ifOutErrors to determine the number of packets transmitted and received with errors. According to the attached file named"Triple Speed Ethernet User Guide"

So, kindly send me a design example made using the SOPC Builder to perform the internal MAC local loopback on it.

Thanks

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hi,

I remember that there is register in the MARVELL PHY to control

the RGMII receive/transmit timing. You can try to see them.

regards,

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Hello,

I did not found the detailed datasheet for the MARVELL PHY device, can you send it to me.

Thanks

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I did not found the detailed datasheet for the MARVELL PHY device, can you send it to me.

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You'll need to contact Marvell and sign an NDA to get a hold of their datasheets.