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Yes, but remember the TSE MAC only works for RGMII Gigabit mode but not RGMII 10/100 mode for now.
Information on setting the timing of RGMII interface
6.2.1 Receive Direction
The FPGA can accept clock edge aligned input data by adding pin-delay to the data inputs
ensuring proper DDR sampling. This can be achieved by applying negative hold-time
constraints (e.g. -1.5ns) to the data input pins of the FPGA.
If the pin-delay should not be used, alternatively the PHY can be instructed to add delay to its clock output pin by setting bit 7 of the MDIO register 20. To do so, the following procedure should be followed:
• read register 20
• set bit 7 to enable rx clock pin output delay preserving all other bits
• write register 20
• Issue a software reset to the phy to apply the change, by reading register 0
(CONTROL) and writing it back with bit 15 (reset) set to 1.
6.2.2 Transmit Direction
A typical DDR output implementation supporting multiple speeds in RGMII will provide the
clock edge aligned with the data edge. However, as the board does not implement a board
trace delay, the clock needs to be shifted by 2ns to ensure proper timing at the PHY device
inputs.
This can be done by either implementing a corresponding shift in the FPGA, or by setting the integrated delay transmit option (bit 1) within the MDIO register 20 of the PHY. To set the transmit delay option, the following procedure should be followed.
• read register 20
• set bit 1 to enable tx clock pin input delay preserving all other bits
• write register 20
• Issue a software reset to the phy to apply the change, by reading register 0 (CONTROL) and writing it back with bit 15 (reset) set to 1.
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Hello,
Can we apply these suggested steps on Cyclone III (C120)?
Thanks
Honored Contributor
