R-tile TX interface unclear. readyAllowance=? readyLatency=?

Hi
readyLatency and readyAllowance have different definition.
Kindly refer to Table 18 of Avalon® Interface Specifications:
https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/st-interface-properties.html

For a better example and illustration between readyLatency and readyAllowance, you can refer to Figure 27 of Avalon® Interface Specifications:
https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/data-transfers-using-readylatency-and.html

It does not follow a fixed latency value between the tx_st_ready_o and tx_st_valid_i signals.

Data can be received any time within the value as specified by the Avalon Interface Specifications.

I agreed with you that the R-tile user guide has some mistake.

The timing diagram in Figure 31 of R-tile user guide named the 3 cycles between Ready deassertion until Valid deassertion as 'readyLatency', in fact it is defined as 'readyAllowance' in the Avalon Interface Specs.

I can feedback this mistake to internal Documentation team for correction.

R-tile user guide, section 4.3.1.4. Avalon Streaming TX Interface:

"This interface does not follow a fixed latency between the pX_tx_st_ready_o and pX_tx_stN_dvalid_i signals as specified by the Avalon Interface

Specifications."

It means data can be received any time within the value as specified by the Avalon Interface Specifications.

readLatency: 0-8

readyAllowance: 0-8

There is a note on page 87 of R-tile user guide says:

"Note: This is an additional requirement for the R-tile PCI Express IP core that does not follow the Avalon-ST standard."

So, although Avalon Interface Spec defined 0-8, the R-tile IP accepts readyAllowance up to 16 cycles as it does not follow the Avalon-ST standard.

Q: It's still unclear about the deassertion of the valid between sop and eop. Can I deassert the valid within the readyAllowance or should I continue until the max(16)?

A: Yes, you can deassert the Valid within the readyAllowance without waiting 16 cycles. An example, in Figure 27 of Avalon Interface Spec, in cycle#9 the Valid is deasserted then re-asserted, data D6 and D7 still can be captured (in this case, since readyAllowance=2, it means two more cycle transfers are allowed after ready deasserted).