R-tile TX interface unclear. readyAllowance=? readyLatency=?

There is a note on page 87 of R-tile user guide says:

"Note: This is an additional requirement for the R-tile PCI Express IP core that does not follow the Avalon-ST standard."

So, although Avalon Interface Spec defined 0-8, the R-tile IP accepts readyAllowance up to 16 cycles as it does not follow the Avalon-ST standard.

Q: It's still unclear about the deassertion of the valid between sop and eop. Can I deassert the valid within the readyAllowance or should I continue until the max(16)?

A: Yes, you can deassert the Valid within the readyAllowance without waiting 16 cycles. An example, in Figure 27 of Avalon Interface Spec, in cycle#9 the Valid is deasserted then re-asserted, data D6 and D7 still can be captured (in this case, since readyAllowance=2, it means two more cycle transfers are allowed after ready deasserted).