Contributor
ContributorIt does not follow a fixed latency value between the tx_st_ready_o and tx_st_valid_i signals.
Data can be received any time within the value as specified by the Avalon Interface Specifications.
ContributorCould you please read again my question and the R-tile doc?
Once more, the R-tile doc is mixing both and is very unclear.
It says readyLatency but what is shown on the diagram is readyAllowance.
The application must not deassert tx_st_valid_i between tx_st_sop_i and tx_st_eop_i on a ready cycle unless there is backpressure from the R-tile PCIe IP indicated by the deassertion of tx_st_ready_o. For the definition of a ready cycle, refer to the Avalon Interface Specifications.
What does that mean? the real tx_st_ready_o signal or it must not deassert the valid between sop and eop considering the readyAllowance?
The R-tile documentation is too confusing and seems wrong on the terms that are used.
I don't understand the purpose of making it so complicated, why not generating the correct ready signal for good instead?!
