R-tile TX interface unclear. readyAllowance=? readyLatency=?

I agreed with you that the R-tile user guide has some mistake.

The timing diagram in Figure 31 of R-tile user guide named the 3 cycles between Ready deassertion until Valid deassertion as 'readyLatency', in fact it is defined as 'readyAllowance' in the Avalon Interface Specs.

I can feedback this mistake to internal Documentation team for correction.