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alexislms's avatar
alexislms
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3 years ago

R-tile TX interface unclear. readyAllowance=? readyLatency=?

R-tile user-guide: https://www.intel.com/content/www/us/en/docs/programmable/683501/22-2-6-0-0/streaming-tx-interface-tx-st-ready-o.html > Refer to the Avalon® Interface Specifications for a deta...
skbeh's avatar
skbeh
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3 years ago

R-tile user guide, section 4.3.1.4. Avalon Streaming TX Interface:

"This interface does not follow a fixed latency between the pX_tx_st_ready_o and pX_tx_stN_dvalid_i signals as specified by the Avalon Interface

Specifications."

It means data can be received any time within the value as specified by the Avalon Interface Specifications.

readLatency: 0-8

readyAllowance: 0-8


  • alexislms's avatar
    alexislms
    Icon for Contributor rankContributor
    3 years ago
    I'l confused because the doc says:

    The maximum latency between the deassertion of tx_st_ready_o and tx_st_valid_i is 16 cycles.

    0-8 or 0-16?

    It's still unclear about the deassertion of the valid between sop and eop. Can I deassert the valid within the readyAllowance or should I continue until the max (16)?