Forum Discussion
alexislms
Contributor
ContributorR-tile TX interface unclear. readyAllowance=? readyLatency=?
R-tile user-guide: https://www.intel.com/content/www/us/en/docs/programmable/683501/22-2-6-0-0/streaming-tx-interface-tx-st-ready-o.html
> Refer to the Avalon® Interface Specifications for a deta...
skbehContributor
ContributorI agreed with you that the R-tile user guide has some mistake.
The timing diagram in Figure 31 of R-tile user guide named the 3 cycles between Ready deassertion until Valid deassertion as 'readyLatency', in fact it is defined as 'readyAllowance' in the Avalon Interface Specs.
I can feedback this mistake to internal Documentation team for correction.
- alexislmsCould you tell the value of each one and answer on the deassertion of the valid?
