Quartus synthesizes my scfifo as a black hole

I've been struggling with a design using a fifo and think I found a bug in the synthesizer. I'm using a very small single clock fifo (8*2 bits) instantiated many times in a component. As it wasn't working I started to put signaltap probes and soon realized that the fifo was always reporting empty=1 even when I was writing to it. After further investigation I found out that the usedw vector is updated correctly when I write to it, it's just the empty signal that is wrong.

I managed to reproduce the problem in a very simple project with only the fifo instantiation. My project is with an EP4CE75F23I7 and here is the code (top level):

library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity testfifo is
  port (
      aclr  : in std_logic ;
      clock : in std_logic ;
      data  : in std_logic_vector (1 downto 0);
      rdreq : in std_logic ;
      empty : out std_logic ;
      q : out std_logic_vector (1 downto 0);
      wrreq : in std_logic 
  );
end entity testfifo;
architecture RTL of testfifo is
  begin
  
      FifoInst : scfifo
    generic map (
      add_ram_output_register => "OFF",
      intended_device_family => "Cyclone IV E",
      lpm_numwords => 8,
      lpm_showahead => "ON",
      lpm_type => "scfifo",
      lpm_width => 2,
      lpm_widthu => 3,
      overflow_checking => "ON",
      underflow_checking => "ON",
      use_eab => "OFF"
    )
    port map (
      aclr => aclr,
      clock => clock,
      data => data,
      rdreq => rdreq,
      wrreq => wrreq,
      empty => empty,
      q => q
    );
end RTL;

When I look into the RTL viewer inside the 'a_fefifo:fifo_state' entity that generates the full and empty signals, I get the picture shown in attachment. No wonder I don't see any change in my empty signals :D

I haven't seen any warning about optimizing things away, and the FIFO works as intended when I set use_eab to "ON" so it really looks like a bug.

Can anyone reproduce this? I'd like to be sure it's nothing wrong with my installation before I file a SR. I'm using Quartus II 11.1 SP2 64 bits (subscription edition).

Putting use_eab to "ON" isn't a solution for me because I'm already low on M9K blocks in my design. Besides I don't like the idea of using a 9kbits block to hold 16 bits ;) If I don't find a quick solution to this I'll either write my own fifo or use the usedw vector instead of the empty signal to detect if the fifo has any data.

Thanks!