Quartus synthesizes my scfifo as a black hole

I filed an SR and it turns out there were two unrelated problems.

First, the RTL view is wrong. With the above project, if you have a look at the technology map viewer, you will see that the logic that generates the empty and full signals is in fact generated, and if you run the FPGA you will see that the FIFO runs correctly. So it looks like the RTL viewer can't always be trusted.

As for my FIFO problem, I still don't know what is causing it. But when I tried to copy the project to simplify it and send an archive to Altera, I realized that it worked fine again. It turns out that deleting the db folder solves the problem, and now it works fine with both use_eab to ON or OFF. There must be something in my db that causes a bad optimisation when I put the use_eab to OFF... Anyway, problem solved, even if I still don't know the cause.