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Altera_Forum
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13 years ago

Quartus synthesizes my scfifo as a black hole

I've been struggling with a design using a fifo and think I found a bug in the synthesizer. I'm using a very small single clock fifo (8*2 bits) instantiated many times in a component. As it wasn't wo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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So it looks like the RTL viewer can't always be trusted.

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I confess to be surprized, It seems like I have to correct my naive view on the RTL netlist viewer. Good to know.

Regards,

Frank