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Altera_Forum
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13 years ago

Quartus synthesizes my scfifo as a black hole

I've been struggling with a design using a fifo and think I found a bug in the synthesizer. I'm using a very small single clock fifo (8*2 bits) instantiated many times in a component. As it wasn't wo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I forgot to post a follow-up on this, but after putting an SR with Altera they agreed there was a problem in the RTL viewer and said it would be fixed in a later version.

I always assumed that the RTL viewer showed exactly the state of the design between the Analysis and Synthesis and the Fitter steps, but in fact it looks like Quartus is taking some short cuts with some internal IP's. It's good to know!