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FabianL's avatar
FabianL
Icon for Occasional Contributor rankOccasional Contributor
4 months ago
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Qsys: EMIF IP Core: usr_reset associated Clock

Hello,

I am a bit confused by the Usage of the emif_usr_reset_n signal of the Intel EMIF IP Core. I have added a EMIF IP Core to our Platform Designer project.

Based on the Documentation (4.1.1.14. emif_usr_reset_n for DDR3) I would assume the usr_reset output to have an associated clock (emif_usr_clk) with a synchronous deassertion:

However in Platform Designer this reset appears without any associated clock and I get reset adapters when assigning it to reset inputs which require synchronous deassertion.

I tried to explicitly set the emif_usr_reset_n output associated clock and synchronous edge, by applying this setting:

But then I end up with the following Warning and I can also confirm, that the corresponding emif.ip file does not have the expected associated clock setting.

So my question is:

  1. Is the documentation (4.1.1.14. emif_usr_reset_n for DDR3) correct and is the emif_usr_reset_n output really synchronous deasserted?
  2. Why does Platform Designer does not recognize the correct clock association for this signal?
  3. How do I configure the IP in a correct way to avoid any unnecessary or unexpected automatically inserted reset adapter?

best regards

Fabian

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Hps Arch
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 months ago

    Hi Fabian,


    The reset is coming from these:


    ***

    always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin

    if (~async_reset_n_pri) begin

    reset_sync_pri_sdc_anchor <= '0;

    end else begin

    reset_sync_pri_sdc_anchor <= reset_sync_pri_pre_reg;

    end

    end

    ***


    You can run simulation to check the synchronous reset behavior.


    Regards,

    Adzim


5 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi Fabian,


    Do you have any question or feedback in this thread?


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi Fabian,


    The reset is coming from these:


    ***

    always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin

    if (~async_reset_n_pri) begin

    reset_sync_pri_sdc_anchor <= '0;

    end else begin

    reset_sync_pri_sdc_anchor <= reset_sync_pri_pre_reg;

    end

    end

    ***


    You can run simulation to check the synchronous reset behavior.


    Regards,

    Adzim


  • FabianL's avatar
    FabianL
    Icon for Occasional Contributor rankOccasional Contributor
    4 months ago

    Hi Adzim,

    I agree, that I can manually modify the .IP file. But gives me an odd feeling, that this may get overwritten if any other IP parameters are changed.

    The main question is, why the IP file added with "Synchronous edges = none" in the first place? This also happens if I create a fresh clean project and add a new EMIF IP Core to the Platdorm Designer System.

    If the reset has really sync deassertion, I would expect the IP core to be added with the correct settings.

    best regards

    Fabian

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 months ago

    Hi Fabian,


    I think the usr_reset_n signal is async assertion and sync deassertion by default.

    You can try to generate an example design and run the simulation.


    The modification that you made here in Qsys is not updated to IP file.

    What you can do is you need to modify the IP file as well.

    You can open the *.ip file, search for emif_usr_reset_n.

    Look for the associatedclock and synchronousedges a few line under emif_usr_reset_n section.

    Then add the ipxact value will clock name and synchronous edge name.

    This will resolve the warning message.


    Regards,

    Adzim