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FabianL's avatar
FabianL
Icon for Occasional Contributor rankOccasional Contributor
4 months ago
Solved

Qsys: EMIF IP Core: usr_reset associated Clock

Hello, I am a bit confused by the Usage of the emif_usr_reset_n signal of the Intel EMIF IP Core. I have added a EMIF IP Core to our Platform Designer project. Based on the Documentation (4.1.1.14...
Configuration
Hps Arch
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 months ago

    Hi Fabian,


    The reset is coming from these:


    ***

    always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin

    if (~async_reset_n_pri) begin

    reset_sync_pri_sdc_anchor <= '0;

    end else begin

    reset_sync_pri_sdc_anchor <= reset_sync_pri_pre_reg;

    end

    end

    ***


    You can run simulation to check the synchronous reset behavior.


    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 months ago

Hi Fabian,


I think the usr_reset_n signal is async assertion and sync deassertion by default.

You can try to generate an example design and run the simulation.


The modification that you made here in Qsys is not updated to IP file.

What you can do is you need to modify the IP file as well.

You can open the *.ip file, search for emif_usr_reset_n.

Look for the associatedclock and synchronousedges a few line under emif_usr_reset_n section.

Then add the ipxact value will clock name and synchronous edge name.

This will resolve the warning message.


Regards,

Adzim