Forum Discussion
Occasional ContributorQsys: EMIF IP Core: usr_reset associated Clock
Hi Fabian,
The reset is coming from these:
***
always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin
if (~async_reset_n_pri) begin
reset_sync_pri_sdc_anchor <= '0;
end else begin
reset_sync_pri_sdc_anchor <= reset_sync_pri_pre_reg;
end
end
***
You can run simulation to check the synchronous reset behavior.
Regards,
Adzim
Regular ContributorHi Fabian,
I think the usr_reset_n signal is async assertion and sync deassertion by default.
You can try to generate an example design and run the simulation.
The modification that you made here in Qsys is not updated to IP file.
What you can do is you need to modify the IP file as well.
You can open the *.ip file, search for emif_usr_reset_n.
Look for the associatedclock and synchronousedges a few line under emif_usr_reset_n section.
Then add the ipxact value will clock name and synchronous edge name.
This will resolve the warning message.
Regards,
Adzim
