Forum Discussion
Occasional ContributorQsys: EMIF IP Core: usr_reset associated Clock
Hi Fabian,
The reset is coming from these:
***
always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin
if (~async_reset_n_pri) begin
reset_sync_pri_sdc_anchor <= '0;
end else begin
reset_sync_pri_sdc_anchor <= reset_sync_pri_pre_reg;
end
end
***
You can run simulation to check the synchronous reset behavior.
Regards,
Adzim
Occasional ContributorHi Adzim,
I agree, that I can manually modify the .IP file. But gives me an odd feeling, that this may get overwritten if any other IP parameters are changed.
The main question is, why the IP file added with "Synchronous edges = none" in the first place? This also happens if I create a fresh clean project and add a new EMIF IP Core to the Platdorm Designer System.
If the reset has really sync deassertion, I would expect the IP core to be added with the correct settings.
best regards
Fabian
