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FabianL's avatar
FabianL
Icon for Occasional Contributor rankOccasional Contributor
4 months ago
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Qsys: EMIF IP Core: usr_reset associated Clock

Hello, I am a bit confused by the Usage of the emif_usr_reset_n signal of the Intel EMIF IP Core. I have added a EMIF IP Core to our Platform Designer project. Based on the Documentation (4.1.1.14...
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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 months ago

    Hi Fabian,


    The reset is coming from these:


    ***

    always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin

    if (~async_reset_n_pri) begin

    reset_sync_pri_sdc_anchor <= '0;

    end else begin

    reset_sync_pri_sdc_anchor <= reset_sync_pri_pre_reg;

    end

    end

    ***


    You can run simulation to check the synchronous reset behavior.


    Regards,

    Adzim


FabianL's avatar
FabianL
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

Hi Adzim,

I agree, that I can manually modify the .IP file. But gives me an odd feeling, that this may get overwritten if any other IP parameters are changed.

The main question is, why the IP file added with "Synchronous edges = none" in the first place? This also happens if I create a fresh clean project and add a new EMIF IP Core to the Platdorm Designer System.

If the reset has really sync deassertion, I would expect the IP core to be added with the correct settings.

best regards

Fabian