problem while displaying D5M image data on LCD using VIP core

Hello,

I went over some of the parameters in the VIP components but I did not find anything critical.

I think for the safe side to configure the CVO FIFO to be at least the line length (800).

Did you try the TPG directly to the CVO and see perfect color bar on the LCD?

BR,

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Hello,

I went over some of the parameters in the VIP components but I did not find anything critical.

I think for the safe side to configure the CVO FIFO to be at least the line length (800).

Did you try the TPG directly to the CVO and see perfect color bar on the LCD?

BR,

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Thank you ra2m ,I've been working all day today but I still couldn't get video displayed on LCD, I tried to add test pattern generator as you suggested and and I got perfect color bar on the LCD, however once I connect the other part of the design I lost the synchronization again. I'm wondering if the problem comes from the DDR because the output of the video custom ip is correct,the output is at 800x600, I also want to ask if the input video frequency should be exactly the same as the output frequency of LCD(33mhz in my case). In my opinion the altera frame buffer ip core will automatically generat the synchronization between two clock domain because I allowed frame dropping and repeating, I tried to decrease the input video frequency and it didn't work out. Is there any other solution for this?

Hello again,

I think that the next step, to debug the system, is to use the TPG and go step by step backward.

Check what happen if you place a 800x600 TPG before the clipper?

Then continue to the next step, put it before the frame buffer. This can give you better understanding if the frame buffer is working.

Regarding input clock and output clock:

If you have Frame buffer with adding and dropping capabilities the clocks do not need to be the same and also there is no need for any relationship between them (in other words – no need for synchronization between them).

Good Luck!

Thank you for updating,

You are welcome.!

Excuse me to ask your help again, I want to replace the Altera VIP megafunction by using other components as the usage of VIP cores are limited and every component is Avalon streaming interface, honestly I have no contribution to the design.

Can I replace the frame buffer ip by SGDMA and FIFOs? how should I connect them into my system, if I don't use Video clock in, I need to create a video buffer to store the pixel into DDR what should I do now, beside the existing Altera IP core, is there other way I can use to realise the video buffering?

Hello Gladys,

I did not succeed to understand what you would like to do?

Do you want to draw graphics using the Nios instead of having a video input? If yes, I suggest you to look at the Frame reader user manual.

BR,

Hi,

You need to understand the VIP Video FB functionality in order design it by your self.

Read the VIP FB user manual.

My recommendation is that and component you decide to design by your self will interface to the Qsys in order to use the DDR memory easily.

I hope this starting point helps you,

BR

If you're comfortable building IP that interfaces with the DDR controller then it's pretty straightforward to create logic that simply moves data into a buffer and pulls it out.

Using the input video timing you can build a capture window that does the clipping function for you, essentially building a new pixel enable for the resolution that you want. Taking advantage of the dual port RAM build a pair of line buffers using your new capture enable signal to store lines of video. Write the data into one line buffer using the input clock while reading the other line into DDR using your memory clock. You can build the buffers out of inferred RAM. I wouldn't mess with FIFOs.

In the DDR you want to double buffer frames so, just like the line buffer, you write one frame while reading out the previous one.

On the output side you essentially build the same thing only it operates in reverse. You need to build a sync generator to create the output timing you want to drive your panel. The resulting pixel enable is used to read the output side of your line buffers. Make sure the active area of your output timing is in the middle of the overall frame so that the DDR has time to pre-load a line and also that you have blanking at the end so you can frame lock.

Frame locking is achieved by sending the input VSync to the output sync generator to tell it when to start a new frame. Until it sees that reference it just keeps adding blanking lines. This means that a line may be cut in half when the reference VSync finally gets there so hopefully your panel doesn't mind. It probably won't but I've used some panels that are very particular about their input timing so it's just a heads up for you. If your panel doesn't like that then you need to do proper frame rate conversion which adds more complexity to the whole thing.