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Hello,
I went over some of the parameters in the VIP components but I did not find anything critical.
I think for the safe side to configure the CVO FIFO to be at least the line length (800).
Did you try the TPG directly to the CVO and see perfect color bar on the LCD?
BR,
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Thank you ra2m ,I've been working all day today but I still couldn't get video displayed on LCD, I tried to add test pattern generator as you suggested and and I got perfect color bar on the LCD, however once I connect the other part of the design I lost the synchronization again. I'm wondering if the problem comes from the DDR because the output of the video custom ip is correct,the output is at 800x600, I also want to ask if the input video frequency should be exactly the same as the output frequency of LCD(33mhz in my case). In my opinion the altera frame buffer ip core will automatically generat the synchronization between two clock domain because I allowed frame dropping and repeating, I tried to decrease the input video frequency and it didn't work out. Is there any other solution for this?
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