Honored Contributor
Honored ContributorIf you're comfortable building IP that interfaces with the DDR controller then it's pretty straightforward to create logic that simply moves data into a buffer and pulls it out.
Using the input video timing you can build a capture window that does the clipping function for you, essentially building a new pixel enable for the resolution that you want. Taking advantage of the dual port RAM build a pair of line buffers using your new capture enable signal to store lines of video. Write the data into one line buffer using the input clock while reading the other line into DDR using your memory clock. You can build the buffers out of inferred RAM. I wouldn't mess with FIFOs. In the DDR you want to double buffer frames so, just like the line buffer, you write one frame while reading out the previous one. On the output side you essentially build the same thing only it operates in reverse. You need to build a sync generator to create the output timing you want to drive your panel. The resulting pixel enable is used to read the output side of your line buffers. Make sure the active area of your output timing is in the middle of the overall frame so that the DDR has time to pre-load a line and also that you have blanking at the end so you can frame lock. Frame locking is achieved by sending the input VSync to the output sync generator to tell it when to start a new frame. Until it sees that reference it just keeps adding blanking lines. This means that a line may be cut in half when the reference VSync finally gets there so hopefully your panel doesn't mind. It probably won't but I've used some panels that are very particular about their input timing so it's just a heads up for you. If your panel doesn't like that then you need to do proper frame rate conversion which adds more complexity to the whole thing.
