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Altera_Forum's avatar
Altera_Forum
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16 years ago

Problem simulating DDR2 SDRAM Controller with ModelSim

I use Quartus 9.0 SP2, ArriaII GX and a DDR2 SDRAM High Performance Controller in my FPGA design.

I have used the EDA Simulation Library Compiler to generate the compiled libraries for ModelSim PE 6.5c and NativeLink to generate a .do file to initialize my ModelSim project.

All the above went well, but went I try to start my simulation I get:

# ** Warning: (vsim-3473) Component instance "regp : dffeas" is not bound.# Time: 0 ps Iteration: 0 Region: /kdarec_tb/b2v_kdarec_top_i/b2v_mctrl_i/mctrl_controller_phy_inst/mctrl_phy_inst/mctrl_phy_mctrl_phy_alt_mem_phy_mctrl_phy_alt_mem_phy_inst_mctrl_phy_alt_mem_phy_dp_io_dpio_mctrl_phy_alt_mem_phy_dq_dqs_dqs_group_0_dq_dqs_18984/dqs_enable_ctrl_inst File: C:/altera/90/quartus/eda/sim_lib/arriaii_atoms.vhd# ** Warning: (vsim-3473) Component instance "regn : dffeas" is not bound.# Time: 0 ps Iteration: 0 Region: /kdarec_tb/b2v_kdarec_top_i/b2v_mctrl_i/mctrl_controller_phy_inst/mctrl_phy_inst/mctrl_phy_mctrl_phy_alt_mem_phy_mctrl_phy_alt_mem_phy_inst_mctrl_phy_alt_mem_phy_dp_io_dpio_mctrl_phy_alt_mem_phy_dq_dqs_dqs_group_0_dq_dqs_18984/dqs_enable_ctrl_inst File: C:/altera/90/quartus/eda/sim_lib/arriaii_atoms.vhd

......

How can I get rid of this problem and RTL simulate my design?

BTW, I don't know if it's related, the EDA Simulation Library Compiler prints the following warning in its log messages:

Warning:# ** Warning: [6] c:/altera/90/quartus/eda/sim_lib/arriaii_atoms.vhd(1781): (vcom-1288) VITAL timing generic "tpd_datainglitch_dataout" port specification "datainglitch" does not denote a port.

and I can't find anywhere in arriaii_atoms.vhd the famous "datainglitch"!

Can some of you Altera gurus please give a hand with this? Thanks.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hello,

    unfortunately for you I am not a guru but some weeks ago I used Modelsim SE 6.5c to simulate DDR2.

    I did not used native link to compile the simulation libraries but I followed the procedure below:

    1) copied the sources of the simulation libraries into a new modelsim project

    2) modified and used the script at page:

    http://www.altera.com/support/examples/download/vhdl-library-setup.tcl?gsa_pos=3&wt.oss_r=1&wt.oss=vhdl%20library%20setup

    (modified because this is for qII 7.1 ad I used qII 9.0 libs)

    3) copied the compiled libs to modelsim directory and edited modelsim.ini to point at them

    I would not suggest you to use this procedure but you may look at the commands used in this script and the ones used in nativelink scripts and spot the differences... Eventually, if guru's answers are on a different timezone, try both variants of the commands. I saw a man use the precompiled libraries from Modelsim Altera in Modelsim SE...

    NOTE: Don't lose time on simulate the DDR2 HP Controller in post synthesis or post place and route... it is based on Altmemphy which can not suppor post synthesis simulation. You will find this info in Altmemphy manual
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi connational,

    I tried your suggestion, now actually doing with your script (modified) the same job NativeLink was supposed to do. I end up with the same error(!)

    I have actually had to manually edit arriaii_atoms.vhd (the one Altera provides!) to fix the bug. Library declarations around line 16791 were wrong and I had to change them to:

    LIBRARY IEEE;

    LIBRARY altera;

    use IEEE.std_logic_1164.all;

    use IEEE.std_logic_arith.all;

    use IEEE.VITAL_Timing.all;

    use IEEE.VITAL_Primitives.all;

    use altera.all;

    use work.arriaii_atom_pack.all;

    This way I got rid of the error ""regn : dffeas" is not bound" etc.

    Now the DDR2 simulates but sadly the local_init_done signal never becomes 1. There must be some other bug...

    I will upgrade to the latest Quartus and DDR2 HP IP and let's see if it helps...

    BTW, I'm just trying functional simulation, not post synthesis, no problem.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    hello... here I can't help you... I simulated on a Stratix III so I did not used arria libs.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Just had to resolve the problem myself too. Problem is that Altera uses a number of different work library names and references some libraries from other libraries by full name, i.e. expecting the dependent libraries to be compiled into a particular work library. I.e., its not enough to compile all Altera simulation libraries into a single Modelsim work library, such as work, but have to actually compile them into particular work libraries.

    In my case, I had to ensure that altera_primitive* was compiled into altera work library, so that stratixiv simulation libraries could find them there (that is the only altera work library stratixiv simulation library references).

    I think it might be worthwhile to compile all of Altera simulation libraries into a single work library, and then vmap it to give it all the expected names.