Problem simulating DDR2 SDRAM Controller with ModelSim

Hi connational,

I tried your suggestion, now actually doing with your script (modified) the same job NativeLink was supposed to do. I end up with the same error(!)

I have actually had to manually edit arriaii_atoms.vhd (the one Altera provides!) to fix the bug. Library declarations around line 16791 were wrong and I had to change them to:

LIBRARY IEEE;

LIBRARY altera;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.VITAL_Timing.all;

use IEEE.VITAL_Primitives.all;

use altera.all;

use work.arriaii_atom_pack.all;

This way I got rid of the error ""regn : dffeas" is not bound" etc.

Now the DDR2 simulates but sadly the local_init_done signal never becomes 1. There must be some other bug...

I will upgrade to the latest Quartus and DDR2 HP IP and let's see if it helps...

BTW, I'm just trying functional simulation, not post synthesis, no problem.