Problem simulating DDR2 SDRAM Controller with ModelSim

Just had to resolve the problem myself too. Problem is that Altera uses a number of different work library names and references some libraries from other libraries by full name, i.e. expecting the dependent libraries to be compiled into a particular work library. I.e., its not enough to compile all Altera simulation libraries into a single Modelsim work library, such as work, but have to actually compile them into particular work libraries.

In my case, I had to ensure that altera_primitive* was compiled into altera work library, so that stratixiv simulation libraries could find them there (that is the only altera work library stratixiv simulation library references).

I think it might be worthwhile to compile all of Altera simulation libraries into a single work library, and then vmap it to give it all the expected names.