New ContributorPCIe stalls
With a large fpga FIFO we include FIFO depth in data streaming to a PC and
see periods of time that the fifo is not being read out on the PCIe (PC) side,
i.e. for every write to the FIFO, the depth increases by one. After a history
of seemingly random PCIe stalls of wildly varying times, which would produce
fifo overflow at our desired transfer rates, we now have more capable hardware
systems and see only very specific and repeatable effects. Specifically, within
about 100KB of the stream start, there's a roughly 5 microsecond stall and then,
about 6.5 MB later, a stall of around 90 microseconds resulting in fifo usage
of 10000+ (512b fifo width and 7.04 GB/s). After these two stalls,
and fifo recovery, the following 24TB transfer completes with the fifo depth remaining
below 20. Because this effect is seen on a variety of PC's, Windows, Linux, as well as
other fpga's, I don't know that hardware details are significant.
Is this a familiar phenomenon?
If I can't do anything about this, it will require additional board-level hardware
and additional gateware complexity to buffer unpredictable amounts of data
(due to use in various systems).
So any information from anyone dealing with this, or even being aware of it,
I would truly appreciate. I have not found any mention of this in all my web searching.
