jsch
New Contributor
2 years agoPCIe stalls
With a large fpga FIFO we include FIFO depth in data streaming to a PC and see periods of time that the fifo is not being read out on the PCIe (PC) side, i.e. for every write to the FIFO, the depth...
Hi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
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