jsch
New Contributor
2 years agoPCIe stalls
With a large fpga FIFO we include FIFO depth in data streaming to a PC and see periods of time that the fifo is not being read out on the PCIe (PC) side, i.e. for every write to the FIFO, the depth...
Hi,
Can I know which device that you are using ?
Which example design are you try to run ? AVST, AVMM or MCDMA ?
Meanwhile,
The phenomenon you're experiencing does sound unusual, especially with the specific and repeatable nature of the stalls. I can offer some suggestions that might help diagnose or mitigate the problem:
Check for PCIe Flow Control: Ensure that the PCIe link is not experiencing flow control issues. If the PCIe link is not able to accept data at the rate it's being sent, it can cause stalls.
Investigate Buffer Management: Look into how the FIFO is managed and if there are any conditions under which it might stall. For example, if there are buffer thresholds that trigger certain behaviors, they could be causing these stalls.
Consider PCIe Latency: PCIe has inherent latency, and depending on how data is being read from the FIFO on the PC side, it's possible that the stalls are related to PCIe transaction latency.
Monitor PCIe Performance Counters: Use PCIe performance counters to monitor the link for errors or anomalies that might indicate issues with the PCIe communication.
Check for Software Delays: Ensure that there are no software delays on the PC side that might cause it to temporarily stop reading from the FIFO.
Consider Using Scatter-Gather DMA: If possible, consider using Scatter-Gather DMA to transfer data to the PC. This can offload some of the data transfer responsibilities from the CPU and may help alleviate stalls.
Update Firmware and Drivers: Ensure that the firmware and drivers for both the FPGA board and the PC are up to date, as older versions might have bugs or limitations that could cause these stalls.
Regards,
Wincent_Intel