PCIe SRIOV VF capabilities

HI,

Based on what I read from the user guide doc, by right the virtual function register (PCI Express Device Capabilities Register) should be the same between physical function (PF) and virtual function (VF)

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf
• page 101 - PCI Express Device Capabilities Register. The VF Device Capabilities Register supports the same fields as the PF Device Capabilities Register.

So, let's take max payload setting for example

• page 85 - reg (0x084) - Maximum Payload Size supported by the Function. Can be configured as 000 (128 bytes) or 001 (256 bytes)
• The setting should follow the max payload setting set in PCIe IP
• page 24 - the only requirement in max payload setting is just to set setting > 128 if used more than 2 PF

May I know where do you see the setting difference in PF vs VF ?

Thanks.

Regards,

dlim

Hi,

Have you review your PCIe software driver to confirm the actual MPS and read request size setting for both PF and VF in PCI Express Device Capabilities Register space ?

Also, what's the MPS setting set in FPGA PCIe hard IP ?

Thanks.

Regards,

dlim

Hi,

According to user guide page 85 (table 58)

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf

PCI Express Device Control and Status Register - 0x088

• Value setting of 0 for both MPS bit [7:5] and RRS bit [14:12] is indeed = 128 bytes
• So did you modify your driver design to change MPS and RRS setting to other larger value beside 0 ?

Another thing to take note is PCI Express Device Capabilities Register -0x084

• bit [2:0] that control Maximum Payload Size supported by the Function
• What's the value setting here ?

Thanks.

Regards,

dlim

Hi,

So far based on all the article that I read so far there is no special control that limit device control register access for VF.

But one thing that I find out is for VF device control register in user guide doc is pointed to 0x048, not 0x088.

• Just wonder have you try to change reg value at 0x048 ?

Thanks.

Regards,

dlim

HI,

Arria 10 and Stratix 10 are having different PCIe reg address space

For A10 : chapter 6.7, figure 48

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf
• device capability = 0x084
• device control = 0x088

For S10 : chapter 8.1.3, figure 66

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avst.pdf
• device capability = 0x074
• device control = 0x078

For you case, I guess you should be changing device control which is 0x078 for S10.

Thanks.

Regards,

dlim

HI,

I don't have any other suggestion for you except following.

I forgot to ask you whether you changed the value in address 0x078 of PF or VF.

• I assume is VF ?

Device control register should be RW register and not RO register. Only device capability register is RO.

• Unless the VF register value is carry forward from PF and can't be edited directly
• Can you try to change the PF 0x078 to see if it bring any changes to VF ?
• If it still doesn't work then likely this is capability limit of VF

Regards,

dlim

HI,

Based on the attached spec pic in previous post, looks like there is no reg control for VF. It will just follow PF reg setting automatically.

In fact, user can't control VF reg

Thanks.

Regards,

dlim