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agula's avatar
agula
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

PCIe SRIOV VF capabilities

Hi, When using virtual functions on the Arria 10 device , I notice that the virtual functions do not have the same maximum read size and maximum payload size as the physical function. Is there a wa...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Have you review your PCIe software driver to confirm the actual MPS and read request size setting for both PF and VF in PCI Express Device Capabilities Register space ?


Also, what's the MPS setting set in FPGA PCIe hard IP ?


Thanks.


Regards,

dlim


agula's avatar
agula
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Yes, I have verified that both MPS and maximum read request size are both 0 at address 0x88 of the virtual function driver. The MPS setting of the FPGA PCIe hard IP is set to 2K, which is correctly reflected in device capabilities for both PF and VF.