Forum Discussion
agula
Occasional Contributor
Occasional ContributorPCIe SRIOV VF capabilities
Hi,
When using virtual functions on the Arria 10 device , I notice that the virtual functions do not have the same maximum read size and maximum payload size as the physical function. Is there a wa...
Deshi_Intel
Regular Contributor
Regular ContributorHI,
Arria 10 and Stratix 10 are having different PCIe reg address space
For A10 : chapter 6.7, figure 48
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf
- device capability = 0x084
- device control = 0x088
For S10 : chapter 8.1.3, figure 66
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avst.pdf
- device capability = 0x074
- device control = 0x078
For you case, I guess you should be changing device control which is 0x078 for S10.
Thanks.
Regards,
dlim
agulaOccasional Contributor
Occasional Contributorwriting to address 0x78 on Stratix 10 has no effect. It seems they are RO parameters that cannot be changed.
I am assuming that 128B is maximum read request size and max payload size allowed by spec. However, I have not been able to get confirmation that this is the case. The information does not seem available at all.
