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agula's avatar
agula
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

PCIe SRIOV VF capabilities

Hi, When using virtual functions on the Arria 10 device , I notice that the virtual functions do not have the same maximum read size and maximum payload size as the physical function. Is there a wa...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


According to user guide page 85 (table 58)


PCI Express Device Control and Status Register - 0x088

  • Value setting of 0 for both MPS bit [7:5] and RRS bit [14:12] is indeed = 128 bytes
  • So did you modify your driver design to change MPS and RRS setting to other larger value beside 0 ?


Another thing to take note is PCI Express Device Capabilities Register -0x084

  • bit [2:0] that control Maximum Payload Size supported by the Function
  • What's the value setting here ?


Thanks.


Regards,

dlim


agula's avatar
agula
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hello,

I tried to program them but they did not update their values. It seems they are set to read only for the Virtual Function. The MPS value at 0x084 is set to 'b100 reflecting a 2K MPS, which is what it is set in the PCIe IP editor.