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Altera_Forum
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13 years ago

PCIe core LTSSM signals

Hi guys,

I've observed some "weird" issue today.

I'm pulling Test_out[4:0] out to my Logic so that I can read them as system status.

When I do that I have intermittent link training issue. Disconnect the lines will make the problem go away.

- Connect those LTSSM bits to my logic: intermittent, failed to nego every 5-6 times

- Disconnect those LTSMM from my logic OR Register them first before feeding into my logic: issue goes away.

Those LTSSM comes directly from HIP, any chance that lots of fanout/delay would cause internal statemachine malfunction?

I repeatedly connect and disconnect the LTSSM from my logic several times and always be able to reproduced.

Baffled by this thing !!!

Thanks a bunch

Jeff

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I've tried to view the LTSSM when the link can't get up, LTSSM goes back and forth between 00000b (detect.quiet) and 00001b (detect.active) ---> what does it mean?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Further probe made me see that the Detect Sequence during Detect.Active substate is not carried out. Somehow, Mr Arria II doesn't output the Voltage stepping and detect the far-end device.... :| frustrated !!!

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I would suggest raising a case at mysupport. If there is a bug, they will report it to be fixed, otherwise they may be able to help you through the problem.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    Are you able to solve your intermittent issue? Also using Arria II device.

    I have similar intermittent ltssm issue during power-on.

    Regards
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Hi,

    Are you able to solve your intermittent issue? Also using Arria II device.

    I have similar intermittent ltssm issue during power-on.

    Regards

    --- Quote End ---

    Mine was an issue caused by the Reset controller in the Reference design. The reset controller has a statemachine which is asynchrnously reset by a signal fed directly from PLL's lock --> The statemachine goes to unknown state sometimes and the HIP can't be initialized properly.

    Exactly where I can't recall. Please trace it first if you still can't find it, I may need to dig up the code.

    Remember, reset controller, PLL's lock signal --> Resolved by a simple synchronization of Reset to the clock domain.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Hi,

    Thanks, is it in the PCIE HIP verilog codes?

    Regards,

    --- Quote End ---

    I'm not sure where exactly.

    https://www.alteraforum.com/forum/attachment.php?attachmentid=7523 https://www.alteraforum.com/forum/attachment.php?attachmentid=7524

    I can't confirm that you have the same issue.

    But here are the signals.

    Look at the last signals in the 2 waveforms. The states variable: ...|calibration|state

    Bad case: the state register goes into some wierd value, everything just stuck there

    Good case: the controller move on after reset is released.

    You can trace that signal
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi jeff,

    I just tried to view the signal to Signal tap. Intermittent power on issue looks same as what you get. Refer to photo.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi jeff,

    I just tried to view the signal to Signal tap. Intermittent power on issue looks same as what you get. Refer to photo.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    Can you tell me which reset signal you synchronize with which clock signal?

    Regards,

    Aris