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Altera_Forum's avatar
Altera_Forum
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13 years ago

PCIe core LTSSM signals

Hi guys, I've observed some "weird" issue today. I'm pulling Test_out[4:0] out to my Logic so that I can read them as system status. When I do that I have intermittent link training issue. D...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Hi,

Thanks, is it in the PCIE HIP verilog codes?

Regards,

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I'm not sure where exactly.

https://www.alteraforum.com/forum/attachment.php?attachmentid=7523 https://www.alteraforum.com/forum/attachment.php?attachmentid=7524

I can't confirm that you have the same issue.

But here are the signals.

Look at the last signals in the 2 waveforms. The states variable: ...|calibration|state

Bad case: the state register goes into some wierd value, everything just stuck there

Good case: the controller move on after reset is released.

You can trace that signal