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Altera_Forum
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14 years ago

PCIe core LTSSM signals

Hi guys, I've observed some "weird" issue today. I'm pulling Test_out[4:0] out to my Logic so that I can read them as system status. When I do that I have intermittent link training issue. D...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Hi,

Are you able to solve your intermittent issue? Also using Arria II device.

I have similar intermittent ltssm issue during power-on.

Regards

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Mine was an issue caused by the Reset controller in the Reference design. The reset controller has a statemachine which is asynchrnously reset by a signal fed directly from PLL's lock --> The statemachine goes to unknown state sometimes and the HIP can't be initialized properly.

Exactly where I can't recall. Please trace it first if you still can't find it, I may need to dig up the code.

Remember, reset controller, PLL's lock signal --> Resolved by a simple synchronization of Reset to the clock domain.