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Altera_Forum's avatar
Altera_Forum
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15 years ago

PCIe BAR size must be larger than Avalon size

I'm using PCIe hard ip with SOPC builder with an Avalon MM conduit to my slave application logic. The size of the memory map on the conduit is 2M so I set my Avalon size in SOPC to 2 pages at 1M each. The SOPC builder does not allow me to set the PCIe BAR size to 2M though. It can't be set to anything lower that 8M otherwise I get the following warning and the BAR size get set to 8M automatically: "

Warning: pcie_compiler_0: bar0_Non_Prefetchable: BAR settings do not allow full access to the mapped Avalon slaves. Avalon size is hardcoded to 2 MBytes - 21 bits and Avalon Base Address is 0x00000000 in PCI Express Compiler settings.'

I can't find any explanation as to why they can't both be set to 2M. Any enlightenment would be appreciated.

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I'm not quite understand your problem, but here is the idea.

    If you have logic, let's say address width of 8.

    PCIe has connection from both bar and TX, then both bar and TX has to be more than width of 8.

    If you just want to use bar access, then you don't need to worry about the translation size, which you are talking about 2M or 1M for 2 pages.

    This is only for the TX interface and will be used for address translation.

    I assume typical design would be something like

    bar 0,1 connects to memory

    bar 2 connects to csr and DMA controller.

    TX interface will be connected to DMA master ports.

    In this case, bar needs to be the size of memory address width.

    TX address translation will be up to your system. Unless you use huge data, 1MB would be enough, usually set it as automatic/dynamic, cause host side software want to set it. Altera PCIe core only can handle 256byte as payload at a time anyway.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for your reply Nekojiru. I think that it is something more fundamental than that though. Even if i setup the PCIe core as 'completer only' so that there is only the slave port and no Tx or CRA port I still get the same warning message as above. My local bus width is 21 bits, but the BAR space automatically gets set to 23 bits.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    My local bus width is 21 bits, but the BAR space automatically gets set to 23 bits.

    --- Quote End ---

    Are your sure that your custom slave component has a memory size of 2MByte ? Can you check that in the SOPC Builder ? A local bus width of 21 bits (I suppose address bus width) does not neccessarily mean 2 MByte address size. The avalon slave address is not a byte address, it is a slave data width address. If your slave has a datawidth of 32 bits then the address is a dword address. A 21 bit dword address corresponds to a 23 bit byte address.