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Altera_Forum
Honored Contributor
Honored ContributorPCIe BAR size must be larger than Avalon size
I'm using PCIe hard ip with SOPC builder with an Avalon MM conduit to my slave application logic. The size of the memory map on the conduit is 2M so I set my Avalon size in SOPC to 2 pages at 1M each...
Altera_ForumHonored Contributor
Honored ContributorI'm not quite understand your problem, but here is the idea.
If you have logic, let's say address width of 8. PCIe has connection from both bar and TX, then both bar and TX has to be more than width of 8. If you just want to use bar access, then you don't need to worry about the translation size, which you are talking about 2M or 1M for 2 pages. This is only for the TX interface and will be used for address translation. I assume typical design would be something like bar 0,1 connects to memory bar 2 connects to csr and DMA controller. TX interface will be connected to DMA master ports. In this case, bar needs to be the size of memory address width. TX address translation will be up to your system. Unless you use huge data, 1MB would be enough, usually set it as automatic/dynamic, cause host side software want to set it. Altera PCIe core only can handle 256byte as payload at a time anyway.
