Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

PCIe BAR size must be larger than Avalon size

I'm using PCIe hard ip with SOPC builder with an Avalon MM conduit to my slave application logic. The size of the memory map on the conduit is 2M so I set my Avalon size in SOPC to 2 pages at 1M each...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for your reply Nekojiru. I think that it is something more fundamental than that though. Even if i setup the PCIe core as 'completer only' so that there is only the slave port and no Tx or CRA port I still get the same warning message as above. My local bus width is 21 bits, but the BAR space automatically gets set to 23 bits.