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NWein's avatar
NWein
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

PCI Express Hard IP on Cyclone 10GX: BARs using I/O space and debug questions

I have a design using the hard PCIe core in a Cyclone 10 GX. First time we're using it. Quartus Prime Pro 19.3.

Two questions:

1) It appears to be impossible to set any of the BAR registers to "I/O Address Space", although it is an option in the pull-down. The user guide says this option was only for legacy endpoints, and that was removed several versions ago. Is it a PCIe thing that you can't set a BAR to I/O space? In past old-style PCI designs we usually used I/O space.

2) Although our link seems to be training OK and we can access the config registers and initialize the BARs, I am seeing no transactions coming out of the rxm_bar<n> interfaces. Are there any good suggestions on how to debug this? I see there is a hip_status bus you can enable, but haven't found any documentation of what the signals actually do. If possible I'd like to be able to confirm whether the read transactions from the CPU are actually being seen by my endpoint. That would be a start at least.

Thanks!

12 Replies

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi ,

    Keeping the post in public.

    May I know which PCIEe IP you are using is it Avalon MM Avalon ST.

    • NWein's avatar
      NWein
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      It's Avalon MM.

      • Rahul_S_Intel1's avatar
        Rahul_S_Intel1
        Icon for Frequent Contributor rankFrequent Contributor
        5 years ago

        Kindly find the inline answers for your question.

        Question no:1

        It is not possible to se the I/O address space in Cyclone 10 GX and for your info the I/O address space is only supported in Legacy endpoint . The Legacy endpoint is only supported in certain variants of Arria 10 devices Avalon ST configuration.

        Below is the error you will get from qsys when you select the I/O address space.

        Error: pcie_a10_hip_0: The current value "I/O address space" for parameter "Type" (bar0_type_hwtcl) is invalid. Possible valid values are: "Disabled" "64-bit prefetchable memory" "32-bit non-prefetchable memory". The parameter value is invalid under these current parameter settings: "Port type" (port_type_hwtcl)="Native endpoint". Rule(s): bar0_type.

        Question:2

        For debugging the PCIe , we have an step by step documentation, in the below link. If you could not able to access the link kindly let me know.

        https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html